The 2008 International Technology Roadmap for Semiconductors, published a year before, showed that scaling was diverging from transistor size. Muller argued that, while Moore’s Law might well deliver billions of transistors, they cannot all be active at the same time without making the chip cook itself to death.
The arrival of dark silicon has taken longer than originally expected, but the problem is getting more pressing as chip designers exhaust their ability to squeeze more efficiency from traditional architectures. Increasingly, the focus is falling on how processors interact with memory.
The core structure they proposed is a non-magnetic layer sandwiched between two magnetic layers. One magnetic layer has a fixed magnetic direction; the other can move freely. When a current passes through the stack from the direction of the fixed layer, the electrons become spin-polarised due to the magnetic field.
If the magnetic fields are not aligned, as carriers pass through the free layer they start to align with the spin of that layer. The reduction in the spin component orthogonal to that of the free layer, through conservation of angular momentum, produces a torque on the layer (see fig 1). This torque can shift the magnetic orientation of the free layer itself. In this way, a magnetic state can be written to it by passing a large enough current through.
Different current profiles can produce oscillations, useful for generating and detecting microwaves, and flip the orientation in the opposite direction. Changes in relative magnetic orientation between the layers restricts current flow to varying degrees, leading to the main use so far for the spin-torque transfer (STT) device as a memory. Everspin started shipping a 256Mbyte magnetic memory (MRAM) based on STT in the summer.
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